Dynamic Random Access Memory (RAM)
Static random access memory devices allow the storage of recorded information as long as power is supplied to the chip. However, the storage cell of SRAM occupies a relatively large area, so for large-capacity RAM, a capacitor is used as the storage cell. The charge on this Capacity naturally decreases over time, so it must be recharged with a period of approximately 10 ms. This period is called the regeneration period. The Capacity is recharged when a memory cell is read, so to regenerate information it is enough to simply read the regenerated memory cell.
The diagram of the dynamic RAM storage element and its design is shown in Figure 1.
Diagram of a dynamic RAM storage element and its design.
When reading the Capacitance charge, it is necessary to take into account that the Capacity of the reading line is much greater than the capacity of the storage cell. Graphs of voltage changes on the read line when reading information from a memory cell without using regeneration are shown in Figure 2.
Figure 2. Graphs of voltage changes on the read line when reading information from a memory cell.
Initially, half of the microcircuit's power is present on the write/read line. To regenerate the initial voltage, the circuit uses an RS trigger connected between two write/read lines. A diagram of such a connection is shown in Figure 3.
Figure 3. Diagram of the regenerating cascade.
To reduce regeneration time, when reading one memory cell in a row of the memory matrix, the entire row is regenerated.
A feature of dynamic RAM is address bus multiplexing. The row address and column address are transmitted alternately. The row address is synchronized by the strobe signal RAS# (Row Address strobe), and the column address is synchronized by CAS# (Column Adress Strobe). Address multiplexing allows you to reduce the number of RAM chip pins. An image of a dynamic RAM chip is shown in Figure 4, and timing diagrams for accessing dynamic RAM are shown in Figure 5.
Figure 4. Illustration of dynamic RAM on circuit diagrams.
Figure 5. Timing diagram of access to dynamic RAM
The timing diagrams shown in the figure assume that when accessing a memory cell, set the code for accessing the RAM memory cell twice on the address bus. Typically, access is made to data located in neighboring memory cells, so it is not necessary to transmit the row address each time when reading. This mode of accessing dynamic RAM is called FPM (Fast Page Mode). The length of the data block read is four words. In order to estimate the time of such a memory access mode, time is measured in processor system bus cycles. In normal memory access mode, the access time is the same for all words. Therefore, the cycle of accessing dynamic memory can be written as 5-5-5-5.
In fast page access mode, the dynamic memory access cycle can be written as 5-3-3-3, that is, the total memory access time is reduced by almost one and a half times. The FPM mode timing diagram is shown in Figure 6.
Figure 6. Timing diagram of access to dynamic RAM in FPM mode.
Another way to increase the speed of RAM is to use EDO (Extended Data Out: RAM with extended data output). In EDO amplifiers, regenerators are not reset at the end of the CAS# strobe, so data reading is faster. For EDO RAM, the dynamic memory access cycle can be written as 5-2-2-2.
The next step in the development of dynamic RAM circuits was the use of a column counter as part of the RAM. That is, when the cell address moves to the next matrix column, the column address is incremented automatically. This RAM is called BEDO (Batch Access RAM).
In synchronous RAM (SDRAM), increased performance is achieved through the use of pipelined signal processing. As you know, when using a pipeline, you can separate individual operations such as fetching rows, fetching columns, reading memory cells, and perform these operations simultaneously. In this case, while the previously read data is being transmitted to the output, the column for the current memory cell is decrypted and the row is decrypted for the next memory cell. This process is illustrated by the following figure:
Figure 7. Block diagram of data processing pipeline.
3.9. Random access storage devices
Storage devices According to the functions performed, they are divided into operational And permanent. Operational storage devices ( RAM) record, store and read information and operate only when the power is on, i.e. RAM are volatile. Permanent storage devices ( ROM) store information when the power is turned off, i.e. ROMs are non-volatile.
Based on the type of information storage, RAM is divided into static And dynamic. In static RAM, the memory element is trigger, in dynamic - capacitor. In English, RAM is called RAM (random access memory- random access memory). Static RAM accordingly SRAM, dynamic DRAM.
Static RAM
On Figure 1 shows the structure of a static storage device.
Fig.1. Static RAM structure
EP is an element of memory. It is also called a storage element ( ZE). All memory elements are contained in the storage matrix. The number of elements is 2 n. Each specific electronic signature stores one bit of information and has its own, specified n- bit binary code.
The address is divided into two parts (usually identical) - a row address and a column address. This results in a rectangular matrix containing 2 k lines and 2 m columns. The total memory elements will be 2 k+m .
Since the number of rows and the number of columns is significantly greater than the bit capacity of a binary number, decoders are placed between the address inputs and the matrix of memory elements, designated in the figure as a row decoder and a column decoder.
Let's consider one of the variants of the static RAM memory element. Here's the diagram:
Rice. 2. Static RAM memory element
The actual element of memory is D-trigger, located at the intersection i-strings and j th column. To reduce the number of chip pins RAM combine their inputs and outputs. Therefore, an electronic key is also included in the diagram S.W..
At levels log. 1 on the lines i And j and when the recording permission signal is given WR=1(from write- record), the trigger records the information that arrives at input D. In this case, the tire Enter exit turns out to be connected to D trigger input via electronic key S.W. and performs input functions when the signal is removed WR the key connects to the bus Enter exit trigger output, and this bus serves as the output.
If the RAM is single-bit, then the bus Enter exit will be common to all memory elements. But more often RAM is multi-bit, and in this case, on each pair of lines, a row-column is located n triggers and n keys where n-the number of digits, and the element "AND" and there is only one left. And each of the keys is connected to its own bus Enter exit.
In addition to the write and read modes, which are determined by the input potential WR, exists data storage mode, in which writing and reading are prohibited. The mode has a double meaning.
Firstly, if the device has many RAM chips, which is typical, then writing or reading is carried out on one chip, the rest in this case should be disabled.
Secondly, in data storage mode, power consumption is much less than in write and read mode ( Work mode). A signal is used to put the RAM into storage mode C.S. in English crystal selection- crystal selection. Usually to switch to storage mode at the input C.S. level is supplied log. 1, to switch to operating mode - log. 0.
Dynamic RAM
As mentioned earlier, in dynamic RAM the functions of a memory element are performed by capacitor. Information is represented by an electric charge, for example, if there is a charge on a capacitor, then it is written to the memory element log. 1, no charge - log. 0.
Since the charge retention time on the capacitor is limited (due to leakage), it is necessary to periodically restore the recorded information. This process is called regeneration. In addition, dynamic RAM requires synchronization to ensure the sequence of activation of functional units.
To implement a dynamic RAM memory element, the circuit shown in Figure 3.
Rice. 3 - Dynamic RAM memory element
The selection of a memory element is made by a signal log. 1 on the line bus. Transistor VT2 opens and connects capacitor C1 with column bus. РШ - bit bus. Previously via transistor VT1, which opens with a signal "Beat (C)", charging capacityWITH w up to tension U 0 . Capacity C w must significantly exceed capacity C1.
The memory element of dynamic RAM is simpler than that of static RAM, so the amount of memory in dynamic RAM is higher than in static RAM. If the address is large, it is divided into two parts. The first one is called RAS, which in English means row access signal- line sampling signal, second - CAS, in English meaning column access signal- column sampling signal.
Signals RAS And CAS shifted relative to each other in time, recording permission signal WR should appear when both parts of the address are entered. At the same time with WR an information signal is introduced. In read mode, the information signal appears at the output with some delay relative to the signal CAS.
Designation of memory chip signals (for information)
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1. Address: A |
2. Clock signal: C |
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3. Column address strobe: CAS |
4. Row address strobe: RAS |
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5. Chip selection: CS |
6. Approval: CE |
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7. Record: WR |
8. Reading: RD |
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9. Write-read: W/R |
10.Recording resolution: WE |
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11.Output resolution: OE |
12.Data (information): D |
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13.Input data: DI |
14.Imprint: DO |
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15.Address, data; input, output: ADIO |
16.Data input, output: DIO |
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17.Regeneration: REF |
18.Programming: PR |
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19.Erase: ER |
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22.General conclusion: OV |
There is much more dynamic memory in a computer than static memory, since DRAM is used as the main memory of the VM. Like SRAM, dynamic memory consists of a core (an array of electronic devices) and interface logic (buffer registers, data reading amplifiers, regeneration circuits, etc.). Although the number of types of DRAM has already exceeded two dozen, their cores are organized almost identically. The main differences are related to the interface logic, and these differences are also due to the scope of application of the microcircuits - in addition to the main memory of the VM, dynamic memory ICs are included, for example, in video adapters. The classification of dynamic memory chips is shown in Fig. 5.10.
To evaluate the differences between types of DRAM, let's first look at the algorithm for working with dynamic memory. For this we will use Fig. 5.6.
Unlike SRAM, the address of a DRAM cell is transferred to the chip in two steps, first the column address and then the row address, which makes it possible to reduce the number of address bus pins by approximately half, reduce the size of the case and place a larger number of chips on the motherboard. This, of course, leads to a decrease in performance, since it takes twice as long to transfer the address. To indicate which part of the address is transmitted at a certain moment, two auxiliary signals RAS and CAS are used. When accessing a memory cell, the address bus is set to the address of the row. After the processes on the bus have stabilized, the RAS signal is applied and the address is written to the internal register of the chip
Rice. 5.10. Classification of dynamic RAM: a - chips for main memory; b - chips for video adapters
memory. The address bus is then set to the column address and the CAS signal is issued. Depending on the state of the WE line, data is read from the cell or written to the cell (the data must be placed on the data bus before writing). The interval between setting the address and issuing the RAS (or CAS) signal is determined by the technical characteristics of the microcircuit, but usually the address is set in one cycle of the system bus, and the control signal in the next. Thus, to read or write one cell of dynamic RAM, five clock cycles are required, in which the following occurs: issuing a row address, issuing a RAS signal, issuing a column address, issuing a CAS signal, performing a read/write operation (in static memory, the procedure takes only two up to three measures).
You should also remember the need to regenerate data. But along with the natural discharge of the capacitor, the electronic device also leads to a loss of charge over time when reading data from DRAM, so after each reading operation the data must be restored. This is achieved by writing the same data again immediately after reading it. When reading information from one cell, the data of the entire selected row is actually output at once, but only those that are in the column of interest are used, and all the rest are ignored. Thus, a read operation from one cell results in the destruction of the entire row's data and must be recovered. Data regeneration after reading is performed automatically by the interface logic of the chip, and this happens immediately after reading the line.
Now let's look at the different types of dynamic memory chips, starting with system DRAM, that is, chips designed to be used as main memory. At the initial stage, these were asynchronous memory chips, the operation of which is not strictly tied to the clock pulses of the system bus.
Asynchronous dynamic RAM. Asynchronous dynamic RAM chips are controlled by RAS and CAS signals, and their operation, in principle, is not directly related to bus clock pulses. Asynchronous memory is characterized by additional time spent on the interaction of memory chips and the controller. Thus, in an asynchronous circuit, the RAS signal will be generated only after a clock pulse arrives at the controller and will be perceived by the memory chip after some time. After this, the memory will produce data, but the controller will be able to read it only upon the arrival of the next clock pulse, since it must work synchronously with the rest of the VM devices. Thus, there are slight delays during the read/write cycle due to the memory controller and memory controller waiting.
MicrocircuitsDRAM. The first dynamic memory chips used the simplest method of data exchange, often called conventional. It allowed reading and writing a memory line only every fifth clock cycle (Fig. 5.11, A). The steps of such a procedure have been described previously. Traditional DRAM corresponds to the formula 5-5-5-5. Microcircuits of this type could operate at frequencies up to 40 MHz and, due to their slowness (access time was about 120 seconds), did not last long.
MicrocircuitsFPM DRAM. Dynamic RAM chips that implement FPM mode are also early types of DRAM. The essence of the regime was shown earlier. The reading circuit for FPM DRAM (Fig. 5.11, b) is described by the formula 5-3-3-3 (14 clock cycles in total). The use of a fast page access scheme has reduced access time to 60 seconds, which, taking into account the ability to operate at higher bus frequencies, has led to an increase in memory performance compared to traditional DRAM by approximately 70%. This type of chip was used in personal computers until about 1994.
MicrocircuitsEDO DRAM. The next stage in the development of dynamic RAM was ICs with hyperpage mode, access(HRM, Hyper Page Mode), better known as EDO (Extended Data Output - extended data retention time at the output). The main feature of the technology is the increased time of data availability at the output of the microcircuit compared to FPM DRAM. In FPM DRAM chips, the output data remains valid only when the CAS signal is active, which is why the second and subsequent row accesses require three clock cycles: a CAS switch to the active state, a data read clock, and a CAS switch to the inactive state. In EDO DRAM, on the active (falling) edge of the C AS signal, the data is stored in an internal register, where it is stored for some time after the next active edge of the signal arrives. This allows the stored data to be used when the CAS is already in an inactive state (Fig. 5.11, V)
In other words, timing parameters are improved by eliminating cycles of waiting for the moment of data stabilization at the output of the microcircuit.
The reading pattern of EDO DRAM is already 5-2-2-2, which is 20% faster than FPM. Access time is about 30-40 ns. It should be noted that the maximum system bus frequency for EDO DRAM chips should not exceed 66 MHz.
MicrocircuitsBEDO DRAM. EDO technology has been improved by VIA Technologies. The new modification of EDO is known as BEDO (Burst EDO). The novelty of the method is that during the first access, the entire line of the microcircuit is read, which includes consecutive words of the package. The sequential transfer of words (switching columns) is automatically monitored by the internal counter of the chip. This eliminates the need to issue addresses for all cells in a packet, but requires support from external logic. The method allows you to reduce the time of reading the second and subsequent words by another clock cycle (Fig. 5.11, d), due to which the formula takes the form 5-1-1-1.
5.11. Timing diagrams of various types of asynchronous dynamic memory with a packet length of four words: a - traditional DRAM; b - FPM FRAM; V- EDO DRAM;
G - BEDO DRAM
MicrocircuitsEDRAM. A faster version of DRAM was developed by Ramtron's subsidiary, Enhanced Memory Systems. The technology is implemented in FPM, EDO and BEDO variants. The chip has a faster core and internal cache memory. The presence of the latter is the main feature of the technology. The cache memory is static memory (SRAM) with a capacity of 2048 bits. The EDRAM core has 2048 columns, each of which is connected to an internal cache. When accessing any cell, the entire row (2048 bits) is read simultaneously. The read line is entered into SRAM, and the transfer of information to cache memory has virtually no effect on performance since it occurs in one clock cycle. When further accesses to cells belonging to the same row are made, the data is taken from the faster cache memory. The next access to the kernel occurs when accessing a cell that is not located in a line stored in the cache memory of the chip.
The technology is most effective when reading sequentially, that is, when the average access time for a chip approaches the values characteristic of static memory (about 10 ns). The main difficulty is incompatibility with controllers used when working with other types of DRAM
Synchronous dynamic RAM. In synchronous DRAM, information exchange is synchronized by external clock signals and occurs at strictly defined points in time, which allows you to take everything from the bandwidth of the processor-memory bus and avoid wait cycles. Address and control information is recorded in the memory IC. After which the response of the microcircuit will occur through a clearly defined number of clock pulses, and the processor can use this time for other actions not related to accessing memory. In the case of synchronous dynamic memory, instead of the duration of the access cycle, they talk about the minimum permissible period of the clock frequency, and we are already talking about a time of the order of 8-10 ns.
MicrocircuitsSDRAM. The abbreviation SDRAM (Synchronous DRAM) is used to refer to “regular” synchronous dynamic RAM chips. The fundamental differences between SDRAM and the asynchronous dynamic RAM discussed above can be reduced to four points:
Synchronous method of data transfer to the bus;
Conveyor mechanism for packet forwarding;
Use of several (two or four) internal memory banks;
Transferring part of the functions of the memory controller to the logic of the microcircuit itself.
Memory synchronicity allows the memory controller to “know” when data is ready, thereby reducing the costs of waiting and searching cycles for data. Since data appears at the output of the IC simultaneously with clock pulses, the interaction of memory with other VM devices is simplified.
Unlike BEDO, the pipeline allows packet data to be transferred clock by clock, thanks to which the RAM can operate uninterruptedly at higher frequencies than asynchronous RAM. The advantages of a pipeline are especially important when transmitting long packets, but not exceeding the length of the chip line.
A significant effect is achieved by dividing the entire set of cells into independent internal arrays (banks). This allows you to combine access to a cell in one bank with preparation for the next operation in the remaining banks (recharging control circuits and restoring information). The ability to keep multiple lines of memory open simultaneously (from different banks) also helps improve memory performance. When accessing banks alternately, the frequency of accessing each of them individually decreases in proportion to the number of banks and SDRAM can operate at higher frequencies. Thanks to the built-in address counter, SDRAM, like BEDO DRAM, allows reading and writing in burst mode, and in SDRAM the burst length varies and in burst mode it is possible to read an entire memory line. The IC can be characterized by the formula 5-1-1-1. Despite the fact that the formula for this type of dynamic memory is the same as that of BEDO, the ability to operate at higher frequencies means that SDRAM with two 6 banks at a bus clock speed of 100 MHz can almost double the performance of BEDO memory.
MicrocircuitsDDR SDRAM. An important step in the further development of SDRAM technology was DDR SDRAM (Double Data Rate SDRAM - SDRAM with double the data transfer rate). Unlike SDRAM, the new modification produces data in burst mode on both edges of the synchronization pulse, due to which the throughput doubles. There are several DDR SDRAM specifications, depending on the system bus clock speed: DDR266, DDR333, DDR400, DDR533. Thus, the peak bandwidth of a DDR333 memory chip is 2.7 GB/s, and for DDR400 it is 3.2 GB/s. DDR SDRAM is currently the most common type of dynamic memory in personal VMs.
MicrocircuitsRDRAM, DRDRAM. The most obvious ways to increase the efficiency of a processor with memory are to increase the bus clock frequency or the sampling width (the number of simultaneously transferred bits). Unfortunately, attempts to combine both options encounter significant technical difficulties (as the frequency increases, the problems of electromagnetic compatibility become worse; it becomes more difficult to ensure that all parallelly sent bits of information arrive at the same time to the consumer). Most synchronous DRAMs (SDRAM, DDR) use wide sampling (64 bits) at a limited bus frequency.
A fundamentally different approach to building DRAM was proposed by Rambus in 1997. It focuses on increasing the clock speed to 400 MHz while reducing the sample width to 16 bits. The new memory is known as RDRAM (Rambus Direct RAM). There are several varieties of this technology: Base, Concurrent and Direct. In all, clocking is carried out on both edges of clock signals (as in DDR), due to which the resulting frequency is 500-600, 600-700 and 800 MHz, respectively. The first two options are almost identical, but the changes in Direct Rambus technology are quite significant.
First, let's look at the fundamental points of RDRAM technology, focusing mainly on the more modern version - DRDRAM. The main difference from other types of DRAM is the original data exchange system between the core and the memory controller, which is based on the so-called “Rambus channel” using an asynchronous block-oriented protocol. At the logical level, information between the controller and memory is transferred in packets.
There are three types of packages: data packages, row packages and column packages. Packets of rows and columns are used to transmit commands from the memory controller to control the rows and columns of the array of storage elements, respectively. These commands replace the conventional chip control system using RAS, CAS, WE and CS signals.
The GE array is divided into banks. Their number in a crystal with a capacity of 64 Mbit is 8 independent or 16 dual banks. In dual banks, the pair of banks share common read/write amplifiers. The internal core of the chip has a 128-bit data bus, which allows 16 bytes to be transferred at each column address. When recording, you can use a mask in which each bit corresponds to one byte of the packet. Using the mask, you can specify how many bytes of the packet and which bytes should be written to memory.
The data, row and column lines in the channel are completely independent, so row commands, column commands and data can be transmitted simultaneously, and for different banks of the chip. Column packets contain two fields and are transmitted over five lines. The first field specifies the main write or read operation. The second field contains either an indication of the use of a record mask (the mask itself is transmitted over the data lines), or an extended operation code that defines an option for the main operation. String packets are divided into activation, cancellation, regeneration and power mode switching commands. Three lines are allocated for transmitting string packets.
The write operation can immediately follow the read - only a delay is needed for the time the signal travels through the channel (from 2.5 to 30, not depending on the length of the channel). To equalize delays in the transmission of individual bits of the transmitted code, the conductors on the board must be positioned strictly in parallel, have the same length (the length of the lines should not exceed 12 cm) and meet strict requirements defined by the developer.
Each write in the channel can be pipelined, with the first data packet having a latency of 50 ns, and the remaining read/write operations occurring continuously (latency is only introduced when changing from a write to a read operation, and vice versa).
Available publications mention the work of Intel and Rambus on a new version of RDRAM, called nDRAM, which will support data transfer at frequencies up to 1600 MHz.
MicrocircuitsSLDRAM. A potential competitor to RDRAM as a memory architecture standard for future personal VMs is a new type of dynamic RAM developed by the SyncLm Consortium, a consortium of VM manufacturers, known by the abbreviation SLDRAM. Unlike RDRAM, the technology of which is the property of Rambus and Intel, this standard is open. At the system level, the technologies are very similar. Data and commands from the controller to memory and back to SLDRAM are transmitted in packets of n or 8 parcels. Commands, address and control signals are sent over a unidirectional 10-bit command bus. Read and write data is supplied over a bidirectional 18-bit data bus. Both buses operate at the same frequency. For now, this frequency is still 200 MHz, which, thanks to DDR technology, is equivalent to 400 MHz. The next generations of SLDRAM should operate at frequencies of 400 MHz and higher, that is, provide an effective frequency of more than 800 MHz.
Up to 8 memory chips can be connected to one controller. To avoid delays in signals from chips further away from the controller, the timing characteristics for each chip are determined and entered into its control register when the power is turned on.
MicrocircuitsESDRAM. This is a synchronous version of EDRAM that uses the same techniques to reduce access time. A write operation, unlike a write operation, bypasses the cache, which increases FSDRAM performance when resuming reading from a line already in the cache. Thanks to the presence of two banks in the chip, downtime due to preparation for read/write operations is minimized. The disadvantages of the microcircuit under consideration are the same as those of EDRAM - the complication of the controller, since it must take into account the possibility of preparing to read a new kernel line into the cache memory. In addition, with an arbitrary sequence of addresses, the cache memory is used inefficiently.
MicrocircuitsCDRAM. This type of RAM was developed by Mitsubishi Corporation, and it can be considered as a revised version of ESDRAM, free from some of its imperfections. The capacity of the cache memory and the principle of placing data in it have been changed. The capacity of a single cache block has been reduced to 128 bits, so the 16-kilobit cache can simultaneously store copies of 128 memory locations, allowing for more efficient use of cache memory. Replacement of the first memory section placed in the cache begins only after the last (128th) block is filled. The means of access have also changed. Thus, the chip uses separate address buses for the static cache and the dynamic core. Transferring data from the dynamic core to cache memory is combined with issuing data to the bus, so frequent but short transfers do not reduce the performance of the IC when reading large amounts of information from memory and put CDRAM on par with ESDRAM, and when reading at selective addresses, CDRAM clearly wins. It should be noted, however, that the above changes led to even greater complexity of the memory controller.
In dynamic storage devices, information is stored in the form of charge on a capacitor. Therefore, power is not supplied to the RAM constantly, but only in very short periods of time. It is used to restore charge on the capacitors of the RAM matrix. Thanks to pulsed power supply, dynamic RAM consumes thousands of times less power than static RAMs of similar capacity.
In dynamic memory chips, the functions of storage elements are performed by electrical capacitors formed inside the MIS structure. Since the time of maintaining the charge on the capacitor is limited, it is necessary to provide for the restoration (regeneration) of the recorded information. The regeneration period for dynamic RAM is several milliseconds (for K565 series microcircuits the regeneration time is 2 ms).
In order to reduce the number of pins, the microcircuits (MCs) of most dynamic RAM are built with multiplexing of the address code: first, the line code A0 - A7 is entered into the MS, fixing it in the input register with a strobe signal RAS ( Row Address Strobe), and then the address code of column A8 - A13, fixing it in the internal register with the strobe signal CAS ( Column Address Strobe).
In regeneration mode, the RAM chip is isolated from the information input and output by applying the CAS = 1 signal. Consequently, only rows are addressed, because information regeneration occurs in all row memory elements simultaneously.
By searching through the addresses of the rows, the regeneration device ensures the restoration of information in the entire matrix of the drive. The symbol of the LSI dynamic RAM type K565RU5 and the timing diagram of the operation are shown in Figure 5.6.
The circuit of a dynamic memory cell with 8 transistors is shown in Figure 5.7. It differs from a similar static RAM cell only in that the gates of transistors T3 and T6 are connected to a regeneration pulse generator, and not to a power source.
 |  |
| Figure 5.7 - Diagram of a dynamic RAM memory cell | Figure 5.8 – Diagram of a single-transistor dynamic RAM cell |
By reducing the number of transistors per cell, it was possible to significantly increase the capacity of dynamic memory located on a single chip and reduce energy consumption from the power source.
5.5. Read-only storage devices
Read-only memory devices (ROM) are non-volatile devices used to store digital data. ROMs can be built on passive elements (fuse links P or diodes D) or active ones (transistors). The ROM circuit is a matrix (Figure 5.9) the number of horizontal lines is equal to the bit depth of the stored word, and the number of vertical lines is equal to the number of stored words.
 | As can be seen from the diagram, when the address line is activated, the vertical bus is connected to the signal ground and the diodes connected to this bus shunt the data lines to ground. Thus, if the horizontal data line is connected to the vertical one through a diode (or jumper), then when selecting the address line, the output of the data line will have a potential close to zero, i.e. logical 0. If the diode or jumper is not present in this node, then at the corresponding output of the data line there is a high potential close to E P, i.e. logical 1. Typically, such ROMs are manufactured with all diodes (or fuses) in the matrix nodes. In those nodes in which a diode or jumper should be missing, they are removed by burning them out. This procedure is performed during ROM programming and is called “ROM burning.” |
| Figure 5.9 – Matrix ROM circuit diagram |
Information is written to ROM word by word (byte by byte). To enter information into a ROM cell, it is necessary to apply a high potential (≈ 25 V) to the data lines, which should contain “1”, and select the appropriate address line, i.e. connect it to signal ground. The current flow melts the diode or fusible link, thereby eliminating the shunt circuit of the corresponding data line.
The disadvantage of the considered ROM circuit is that once information is entered into this device, it cannot be changed. That is, when changing the program to be stored in ROM, it is necessary to program a new device. To overcome this drawback, semi-permanent electrically reprogrammable read-only memories (EEPROMs) have been developed. An EEPROM circuit is similar to a MOSFET ROM, but the transistors in such a device have a floating gate that is electrically insulated by an oxide layer of semiconductor material. The EEPROM circuit is shown in Figure 5.10. When a positive potential is applied to the floating gate (FG) relative to the drain of the transistor, an electric charge is induced on the FG, which, due to high-quality insulation, can last up to 10 years or more. Thanks to this charge, the transistor is in an open state, in which the Drain-Source resistance becomes close to zero.
Dynamic RAM(Dynamic RAM - DRAM) is used in most RAM systems of modern PCs. The main advantage of this type of memory is that its cells are very densely packed, i.e. Many bits can be packed into a small chip, which means that large-capacity memory can be organized on their basis.
The memory cells in a DRAM chip are tiny capacitors that hold charges. This is exactly how the bits are encoded (by the presence or absence of charges). The problems associated with this type of memory are caused by the fact that it is dynamic, i.e. must be constantly regenerated, otherwise the electrical charges in the memory capacitors will “drain” and data will be lost. A refresh occurs when the system's memory controller takes a tiny break and accesses all the data lines in the memory chips. Most systems have a memory controller (usually built into the motherboard chipset, but it can also be built into the processor, as in the Athlon 64 and Opteron processors) that is set to an industry-standard refresh rate of 15 ms. This means that every 15 ms all rows in memory are read to ensure data regeneration.
Memory regeneration, unfortunately, takes time away from the processor. Each regeneration cycle takes several CPU cycles in duration. In older computers, refresh cycles could take up to 10% (or more) of CPU time, but in modern systems this cost is less than 1%. Some systems allow you to change regeneration settings using the BIOS setup utility. The interval between update cycles is called tREF and is specified not in milliseconds, but in clock cycles. It is very important to understand that increasing the interval between update cycles to improve system performance can lead to occasional random errors.
An arbitrary error is a data processing error not related to a defect in the memory chip. In most cases, it is safer to stick to the recommended or default regeneration frequency. Since regeneration costs in modern computers are less than 1%, changing the refresh rate has little impact on the computer's performance. One of the most acceptable options is to use the default values or automatic settings specified using the Setup BIOS program for memory synchronization. Most modern systems do not allow you to change the specified memory timing, always using automatically set parameters.
DRAM devices use only one transistor and a pair of capacitors to store one bit, so they are larger than other types of memory chips. Currently, dynamic RAM chips with a capacity of 4 GB or more are already being produced. This means that such chips contain more than a billion transistors! But the Core 2 Duo processor has only 230 million transistors. Why such a difference? The fact is that in a memory chip all transistors and capacitors are placed in series, usually in the nodes of a square lattice, in the form of very simple, periodically repeating structures, in contrast to the processor, which is a more complex circuit of various structures that does not have a clear organization.
The transistor of each single-bit DRAM register is used to read the state of the adjacent capacitor. If the capacitor is charged, a unit is written in the cell; if there is no charge, a zero is written. Charges in tiny capacitors are constantly draining, so the memory must be constantly regenerated. Even a momentary interruption in power supply or some kind of failure in the regeneration cycles leads to loss of charge in the DRAM cell, and, consequently, to loss of data. In a running system, this leads to the appearance of a “blue screen of death”, global failures of the security system, file corruption, or a complete system failure.
RAM Types and Performance
There is some confusion about memory performance because it is usually measured in nanoseconds, while processor speed is measured in megahertz and gigahertz. In new high-speed memory modules, performance is measured in megahertz, which further complicates the situation. Fortunately, converting one unit of measurement to another is not difficult.
A nanosecond is one billionth of a second, i.e. a very short period of time. In particular, the speed of light in vacuum is 299,792 km/s, i.e. in one billionth of a second, the light beam travels a distance of only 29.98 cm, i.e. less than the length of a regular ruler.
The speed of memory chips and systems in general is expressed in megahertz (MHz), i.e. in millions of cycles per second, or in gigahertz (GHz), i.e. in billions of cycles per second. Modern processors have clock speeds ranging from 2 to 4 GHz, although their internal architecture (such as multi-core) has a much greater impact on their performance.
As the clock frequency increases, the cycle time decreases. During the evolution of computers, to improve memory access efficiency, various levels of caching were created to intercept processor access to slower main memory. Only recently have DDR, DDR2 and DDR3 SDRAM memory modules caught up with the processor bus performance. When the processor and memory bus frequencies are equal, memory performance becomes optimal for a particular system.
By 2000, processor and memory bus speeds had increased to 100 and even 133 MHz (these modules were called PC100 and PC133, respectively). At the beginning of 2001, memory speed doubled and became equal to 200 and 266 MHz; in 2002, DDR memory modules were released at 333 MHz, and in 2003, at 400 and 533 MHz. In 2005 and 2006, the increase in memory speed corresponded to the increase in processor bus speed - from 667 to 800 MHz. In 2007, the speed of DDR2 memory was increased to 1066 MHz, and at the same time DDR3 memory was released with the same and higher frequency. The table below lists the main types of memory modules and their speed.
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EDO. Extended Data Out (extended data output capabilities).
DIMM. Dual Inline Memory Module (memory module with double-row pinout).
DDR. Double Data Rate (double data transfer speed).
FPM. Fast Page Mode (fast page mode).
SIMM. Single Inline Memory Module (memory module with single-row pinout).
RIMM. Rambus Inline Memory Module (memory module of the Rambus standard).
Memory performance
When replacing a faulty memory module or chip, the new element must be of the same type. Typically, problems arise when using chips or modules that do not meet certain (not too numerous) requirements, for example, the duration of regeneration cycles. You may also encounter inconsistencies in pinouts, capacitance, capacity, or design. If you don't know what memory modules your motherboard allows, check your documentation.
When you install faster memory modules, computer performance usually does not improve because the system accesses it at the same frequency. In systems using DIMMs and RIMMs, speed and other timing characteristics are read from a special SPD ROM installed on the module. The memory controller is then configured using these parameters. The performance of such systems can be increased by installing faster memory modules, up to the limit supported by the system logic chipset.
To address timing and reliability issues, Intel and JEDEC have created standards for high-speed memory modules, defining memory module types that meet specific performance levels. According to these standards, memory modules are classified according to their timing characteristics.
The main signs of insufficient memory performance or its inconsistency with the timing characteristics of the system are memory and parity errors, as well as freezing and unstable operation of the system. In this case, the POST test may also throw errors. If you are not sure which memory modules are acceptable for your system, contact your computer manufacturer and try to purchase memory modules from a reputable supplier.
Parity and Error Correction Codes (ECC)
Errors when storing information in RAM are inevitable. These are usually classified as hardware failures and intermittent errors (crashes).
If a normally functioning microcircuit, due to, for example, physical damage, begins to work incorrectly, then this is called a hardware failure. To resolve this type of failure, you usually need to replace some part of the memory hardware, such as a faulty chip, SIMM, or DIMM.
Another, more insidious type of failure is an intermittent error (crash). This is an intermittent failure that does not occur when operating conditions are repeated or at regular intervals. (Such failures are usually “treated” by turning off the computer’s power and then turning it back on.)
About 20 years ago, Intel employees determined that alpha particles were causing the glitches. Since alpha particles cannot penetrate even a thin sheet of paper, it was discovered that their source was a substance used in semiconductors. During the study, particles of thorium and uranium were found in the plastic and ceramic cases of microcircuits used in those years. By changing the technological process, memory manufacturers got rid of these impurities.
Memory manufacturers have now almost completely eliminated sources of alpha particles. As a result, many memory module manufacturers have removed parity check support from their products, despite the fact that memory failures have not been completely eliminated. More recent research has shown that alpha particles account for only a small fraction of the causes of memory failures.
Today, the biggest cause of irregular errors is cosmic rays. Because they are so penetrating, it is almost impossible to protect against them using shielding. This thesis was confirmed by a number of studies conducted by IBM under the leadership of Dr. J.F. Ziegler.
An experiment to test the degree to which cosmic rays influence errors in microcircuit operation showed that the Signal-to-Error Ratio (SER) for some DRAM modules was 5950 Failure Units (FU) per billion hours developments for each microcircuit. The measurements were carried out under conditions close to real ones, taking into account a duration of several million machine hours. On an average computer, this would mean a software memory error occurring approximately every six months. On server systems or powerful workstations with a large amount of installed RAM, statistics like this indicate one (or even more) memory error every month! When a test system with the same DIMMs was placed in a safe shelter at a depth of more than 15 meters under a layer of rock, which completely eliminates the influence of cosmic rays, software errors in the memory were not recorded at all. The experiment demonstrated not only the danger of the influence of cosmic rays, but also proved how effective it is to eliminate the influence of alpha rays and radioactive impurities in the shells of memory modules.
Errors caused by cosmic rays are a greater danger for SRAM modules than for DRAM modules because the charge required to store one bit in an SRAM cell is much less than the capacitor capacity in DRAM. Cosmic rays also pose a greater threat to high-density memory chips. The higher the density of memory cells, the higher the probability that a cosmic ray will hit such a cell. As the memory size increases, the error rate also increases.
Unfortunately, PC manufacturers have not recognized this as a cause of memory errors. The random nature of the failure is much easier to justify as electrostatic discharge, large power surges, or erratic software operation (for example, using a new version of the operating system or a large application program). Studies have shown that for ECC systems, the proportion of software errors is 30 times greater than hardware errors. And this is not surprising, given the harmful effects of cosmic rays. The number of errors depends on the number of installed memory modules and their size. Software errors can happen once a month, several times a week, and even more often.
Although cosmic rays and radiation are the cause of most software memory errors, there are other factors.
Power surges or line noise. The cause may be a faulty power supply or wall outlet.
Using memory with incorrect type or characteristics. The memory type must be supported by a specific chipset and have an access speed defined by that set.
Static discharges. Cause instant surges in power supply, which can affect data integrity.
Synchronization errors. Data not received in a timely manner may cause software errors. Often the reason is incorrect BIOS settings, RAM that is slower than the system requires, overclocked processors, and other system components.
Heat dissipation. High-speed memory modules are characterized by higher operating temperatures than legacy modules. The first modules equipped with heat dissipators were RDRAM RIMM modules; Nowadays, many high-performance DDR2 and DDR3 modules are equipped with heat dissipators, since this is the only way to combat the increased level of heat generation.
Most of the problems described do not cause memory chips to stop working (although poor power supply or static electricity can physically damage them), but they can affect stored data.
Ignoring failures, of course, is not the best way to deal with them. To improve fault tolerance, modern computers use techniques such as parity and error correction codes (ECC).
Systems without parity provide no fault tolerance at all. The only reason they are used is their minimum base cost. At the same time, unlike other technologies, additional RAM is not required. A parity data byte contains 9 rather than 8 bits, so the cost of parity memory is approximately 12.5% higher. In addition, memory controllers that do not require logic bridges for parity or ECC data have a simplified internal architecture. Portable systems, where low power consumption is particularly important, benefit from reduced memory power due to the use of fewer DRAM chips. Finally, the memory data bus without parity has a smaller width, which translates into fewer data buffers. The statistical probability of memory errors occurring in modern desktop computers is approximately one error every few months. The number of errors depends on the amount and type of memory used.
This error rate may be acceptable for regular computers not used for critical applications. In this case, price plays a major role, and the additional cost of memory modules with parity and ECC support is not justified, so it is easier to accept infrequent errors.
Parity
This is one of the standards introduced by IBM, according to which information in memory banks is stored in fragments of 9 bits, with eight of them (comprising one byte) being intended for data itself, and the ninth being a parity bit. The use of the ninth bit allows hardware-level memory management circuits to monitor the integrity of each byte of data. If an error is detected, the computer stops and a fault message appears on the screen. If you are working on a computer running Windows or OS/2, if a parity error occurs, the message may not appear, but the system will simply lock up. After rebooting, the BIOS should identify the error and display a corresponding message.
SIMMs and DIMMs come with or without parity bit support.
The first PCs used parity memory to regulate the accuracy of the operations performed. Beginning in 1994, a disturbing trend began to develop in the PC market. Most companies began offering computers with memory without parity and without any means of detecting or correcting errors. The use of SIMM modules without parity reduced memory costs by 10–15%. In turn, parity memory was more expensive due to the use of additional parity bits. Parity technology does not correct system errors, but it does provide the computer user with the ability to detect them, which has the following advantages:
Parity control protects against the consequences of incorrect calculations based on incorrect data;
Parity checks pinpoint the source of errors, helping you understand the problem and improving your computer's operational reliability.
Implementing memory support with or without parity requires little effort. In particular, implementing parity support for a motherboard is not difficult. The main implementation costs are related to the cost of the parity memory modules themselves. If buyers are willing to incur additional costs to improve the reliability of the systems they order, computer manufacturers can provide them with this option.
Parity check scheme
When developing the parity standard, IBM specified that the value of the parity bit is set so that the number of ones in all nine bits (eight data bits and the parity bit) is odd. In other words, when a byte (8 bits) of data is written into memory, a special parity circuit (a chip installed on the motherboard or memory card) counts the number of ones in the byte. If it is even, a logical one signal is generated at the output of the microcircuit, which is stored in the corresponding memory bit as the ninth bit (parity bit). The total number of ones in all nine digits becomes odd. If the number of ones in eight bits of the source data is odd, then the parity bit is zero, and the sum of the binary digits in nine bits also remains odd.
Let's look at a specific example (keep in mind that the bits in a byte are numbered starting from zero, i.e. 0, 1, 2, ..., 7).
Bit value: 1 0 1 1 0 0 1 1 0
In this case, the total number of one data bits is odd (5), so the parity bit must be zero.
Let's look at another example.
Data bit: 0 1 2 3 4 5 6 7 parity bits
Bit value: 0 0 1 1 0 0 1 1 1
In this example, the total number of 1's data bits is even (4), so the parity bit must be set to 1 in order for the number of 1's in all nine bits to be odd.
When reading from memory, the same chip checks the information for parity. If there is an even number of ones in a 9-bit byte, then an error occurred while reading or writing data. It is impossible to determine in which discharge it occurred (you cannot even find out the number of damaged discharges). Moreover, if a failure occurred in three bits (an odd number), then the error will be recorded; however, if there are two erroneous bits (or an even number of them), the failure is not recorded. Since a simultaneous error in several bits of one byte is extremely unlikely, this testing scheme was inexpensive and at the same time made it possible to detect errors in memory with a high probability.
When an error is detected, the parity circuitry on the system board generates a non-maskable interrupt (NMI), a system warning that programs cannot ignore. The main work stops and a special procedure written in the BIOS is initiated.
Just a few years ago, when memory was expensive, some companies released SIMMs with dummy parity check chips. Instead of storing parity bits for each byte of memory, these chips always generated the correct complement bit. Thus, when the system tried to write a parity bit, it was simply discarded, and when reading a byte, the “necessary” parity bit was always substituted. As a result, the system always received information about the correct operation of the memory, although in reality everything could be far from being so.
Such scams were caused by the high cost of memory chips, and manufacturers were willing to pay a couple of extra dollars on the generator rather than pay for the more expensive chip that stores the parity bits. Unfortunately, it was quite difficult to determine the presence of such a generator in a memory module. The fake parity generator looked different from regular memory chips and had different markings from other module chips. Most of the generators had a “GSM” logo, which indicated the manufacturer of the parity logic device, often different from the company that produced the memory module itself.
The only tool that made it possible to identify modules with fake parity checks was hardware testers. Now memory prices have fallen, which has eliminated the root cause of such fraud.
Error correction code
Error Correcting Codes (ECC) allow you to not only detect an error, but also correct it in one bit. Therefore, a computer that uses such codes can operate without interruption in the event of an error in one bit, and the data will not be corrupted. The error correction codes on most PCs can only detect, but not correct, two-bit errors. At the same time, approximately 98% of memory failures are caused by an error in one bit, i.e. it can be successfully fixed using this type of code. This type of ECC is called SEC_DED (this abbreviation stands for “one-bit correction, two-bit error detection”).
In error correction codes of this type, for every 32 bits, an additional seven check bits are required for a 4-byte organization and eight for an 8-byte organization (64-bit Athlon/Pentium processors). Implementing error correction code with a 4-byte organization is naturally more expensive than a regular parity check, but with an 8-byte organization their costs are equal, since they require the same number of additional bits.
To use error correction codes, a memory controller is required that calculates check bits during a memory write operation. When reading from memory, such a controller compares the read and calculated values of the check bits and, if necessary, corrects the damaged bit (or bits). The cost of additional logic circuitry to implement error correction code in the memory controller is not very high, but it can significantly reduce memory performance during write operations. This is because write and read operations must wait for the check bits to complete. When writing part of a word, you must first read the full word, then rewrite the modified bytes, and only after that, the new calculated check bits.
In most cases, memory failure occurs in a single bit, and therefore such errors are successfully corrected using error correction code. The use of fault-tolerant memory ensures high computer reliability. ECC memory is intended for servers, workstations, or applications where the potential cost of a computation error far outweighs the additional hardware investment and system time required. If data is of special importance and computers are used to solve important problems, ECC memory is indispensable. In fact, no self-respecting systems engineer would use a server, even the most unpretentious one, without ECC memory.
Users have a choice between non-parity, parity and ECC systems, i.e. between the desired level of computer fault tolerance and the degree of value of the data used.
Conclusion
To use error correction codes, a memory controller is required that calculates check bits during a memory write operation. The cost of additional logic circuitry to implement error correction code in the memory controller is not very high, but it can significantly reduce memory performance during write operations. This is because write and read operations must wait for the check bits to complete.
The use of fault-tolerant memory ensures high computer reliability. ECC memory is intended for servers, workstations, or applications where the potential cost of a computation error far outweighs the additional hardware investment and system time required. If data is of special importance and computers are used to solve important problems, ECC memory is indispensable.
